Expand description
Scheduling information for each opcode
Structs§
- Exec
Ports 🔒 - Identify one or more CPU execution ports
Constants§
- MAX_
LATENCY 🔒 - Maximum value of
instruction_latency_cycles()for any Opcode - NUM_
EXECUTION_ 🔒PORTS - Number of execution ports in our simulated microarchitecture
- P0 🔒
- Port P0 (second choice) only
- P01 🔒
- Either port P0 or P1
- P015 🔒
- Any of the three ports
- P05 🔒
- Either port P0 or P5
- P1 🔒
- Port P1 (third choice) only
- P5 🔒
- Port P5 (first choice) only
- SCHEDULE_
SIZE 🔒 - Total number of cycles to store schedule data for
- TARGET_
CYCLES 🔒 - Number of simulated cycles we run before stopping program generation
Functions§
- instruction_
latency_ 🔒cycles - Latency for each operation, in cycles
- instruction_
sub_ 🔒cycle_ count - Each instruction advances the earliest possible issuing cycle by one sub-cycle per micro-op.
- micro_
operations 🔒 - Break an instruction down into one or two micro-operation port sets.