Module scheduler 

Scheduling model for program generation

HashX uses a simple scheduling model inspired by the Intel Ivy Bridge microarchitecture to choose registers that should be available and avoid stalls.

Modules

model 🔒

Scheduling information for each opcode

Structs

Cycle 🔒

Cycle timestamp

DataSchedule 🔒

Latency tracking for all relevant CPU registers

ExecPortIndex 🔒

One single execution port

ExecSchedule 🔒

Execution schedule for all ports

InstructionPlan 🔒

Detailed execution schedule for one instruction

MicroOpPlan 🔒

Detailed execution schedule for one micro-operation

PortSchedule 🔒

Busy tracking for one CPU execution port

Scheduler 🔒

Overall state for the simulated execution schedule

SimpleBitArray 🔒

Simple packed bit array implementation

SubCycle 🔒

Sub-cycle timestamp